The greatest benefit to simulating sensors is the ability to push past the operational limits of a specific environment and test fault conditions that would otherwise be damaging or dangerous, giving your test higher coverage with lower risk. You can implement and test changes to system components without fear of destroying expensive equipment. For example, you can verify an engine control unit (ECU) without running an actual engine at high temperatures for extended periods of time. The simulated signals can range from simple analog waveforms to custom digital protocols. By taking advantage of inherent parallel processing, field-programmable gate array (FPGA) hardware provides the performance and flexibility to simultaneously simulate a variety of sensors in real time.

FPGAs are ideal for sensor simulation, primarily because they can adapt to multiple sensor types with precise timing requirements. You can customize each sensor output down to nanoseconds and completely synchronize various signals to realistically create a specific state of operation. In many cases, however, sensors function independently and update at different rates. With the true parallel nature of FPGAs, dedicated blocks of silicon also can operate without any interference from other parts of the application.

While the majority of sensors produce an analog signal based on their measurements, there are many sensors that convey information digitally, using methods such as pulse-width modulation or serialized protocols. An FPGA-based approach can easily integrate the processing required to generate complex digital signals as well as arbitrary analog waveforms without affecting the performance of other tasks in the application.

A linear variable differential transformer (LVDT) is a sensor that incorporates a differential transformer with a sliding magnetic core. Driven by an AC excitation source, the LVDT generates a pair of AC output signals that are modulated according to the mechanical position (displacement) of the core. The ideal output of an LVDT without signal conditioning is a scaled version of the excitation signal. This scaling factor can be positive or negative and is proportional to the distance from the mechanical middle of the device. The host computer passes the displacement in the form of a scaling factor to multiply with either the generated or real-world excitation signal. The host VI uses inputs of simulated position and desired sensitivity to calculate a scaling factor. This is passed to the FPGA through the Sim LVDT Scaling variable. Figure 1 is the graphical host interface subVI for LVDT simulation.

On the FPGA, you can programmatically decide whether to use internal or external excitation and pass the value through the shift register to the multiplier and bit refactoring. This applies the appropriate scaling to the signal based on the simulated displacement and finally asserts the data point to an analog output channel. The technique of passing the data to the next iteration is the graphical method of pipelining for FPGA optimization. With the new noise generator Express VI in LabVIEW 8.5, you can even add some noise to the output to give your DUT a more realistic simulation.

With the release of LabVIEW 8.5, you can find this LVDT example as well as other sensor simulation IP blocks at the new FPGA IPNet online. Similar to the Instrument Driver Network (ni.com/idnet), IPNet is a site (ni.com/ipnet) for searching, downloading, and even sharing FPGA IP in the form of modular functions or complete FPGA examples.

To view a 10-minute Webcast on the new features of in the LabVIEW 8.5 FPGA Module, go to www.ni.com/info and enter nsi7303.

This article first appeared in the Q3 2007 issue of Instrumentation Newsletter. Rick Kuhlman is a product manager for LabVIEW FPGA. Vineet Aggarwal is a product manager for intelligent NI data acquisition products.
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